1. Field
The present invention relates to means for digitally encoding and decoding RF signals and, more particularly, to the encoding and decoding of pulsed, high frequency, RF signals using a minimum number of bits.
2. Prior Art
A well known system incorporating a delay line for encoding, storing and reproducing an RF signal is illustrated in FIG. 7. The apparatus in this Figure comprises a receiver 701, a Switch 702, an Amplifier 703, a Circulating Delay Line 704, and a Switch 705. In the operation of this system, a received RF signal is passed from the Receiver 701 through the First Switch 702 and Amplifier 703 into the Delay Line 704 which circulates the received signal back through Amplifier 703 and then back to the beginning of the Delay Line. The circulating signal may be sampled at output port 706 at the output of the Second Switch 705. A signal once admitted to the Delay Line tends to circulate about the Delay Line until it is overridden by noise, which typically occurs within ten circulations through the line.
A second prior art system, shown in FIG. 8 comprises a Receiver 801, a Discriminator 802, a Storage Unit 803, a Comparator 804, a Voltage Controlled Oscillator 805, a Switch 806, and a Switch 807.
In the operation of this system, a signal transmitted from the Receiver to the Discriminator 802, produces an output voltage that is placed into storage by way of Switch 807. To reproduce the received signal, the stored voltage (or its digital equivalent) is supplied to the Comparator. Switches 806 and 807, which are ganged, are then set to the position which transmits the output of the Discriminator to the Comparator. The Comparator output is fed to the Oscillator 805 for use as a frequency control voltage. The Oscillator output is fed back by way of Switch 806 to the Discriminator 802.
The combination of the Discriminator, Comparator and Oscillator, arranged to transmit the output of the Voltage Controlled Oscillator back to the Discriminator, forms a feedback loop which causes the Oscillator to be driven to the frequency which produces the same discriminator output voltage as was produced by the original signal. In this way, the Oscillator is caused to operate at or near the frequency of the received signal.
The accuracy to which this system can reproduce the original signal is limited by the resolution of the Discriminator which may typically range from one to five percent of the Discriminator bandwidth. If the Discriminator is of the type that includes rectifiers and filters, a number of cycles are required before the Discriminator can produce an output voltage at the frequency of the received signal. Where a pulsed signal is applied to the Discriminator, the delay in producing the output voltage may be so long as to prevent arriving at the final value. Discriminators that are capable of providing an instantaneous output are available; however, the instantaneous feature solves only one problem. The resolution of such Discriminators is not necessarily improved over those Discriminators which take a longer period of time to arrive at a final output level.
There are, in addition, other significant sources of error. The Voltage Controlled Oscillators in these circuits drift and there is an error voltage inherent in the feedback loop, both of which add to the error caused by the Discriminator's resolution and drift, affecting the final reproduction of the signal frequency by this system. Where a received pulse contains FM modulation, this system is entirely inadequate to properly process such a signal.
A third type of prior art system commonly referred to as a phase locked system is shown in FIG. 9. In this Figure, the system is shown to comprise a Receiver 901, a Phase Detector 902, and a Voltage Controlled Oscillator 903.
In the operation of this system, a signal from the output of the receiver is fed to the Phase Detector. The DC output 904 of the Phase Detector is used to control a Voltage Controlled Oscillator whose RF output 905 is returned to the Phase Detector. The output of the Phase Detector drives the Voltage Controlled Oscillator to the frequency of the incoming signal from the receiver.
The deficiencies of the system shown in FIG. 8 generally apply to the phase locked system as well. In addition, there is no storage provided for the received signal. Once the input signal has been removed, there is no means provided for retaining the signal. This defect can be remedied by adding a memory which stores the final control voltage produced by the Phase Detector. However, any drift in the Voltage Controlled Oscillator, after the input signal has been removed, adds directly to the error in the frequency of the replicated signal.
A fourth type of prior art system generally referred to as a digital sampling system is shown in FIG. 10. In this Figure, a square wave 1003 is plotted on a coordinate axis consisting of an ordinate 1001 representing amplitude, and an abscissa 1004 representing time.
In this system, continuous samples of a constant amplitude square wave are taken. The samples are represented by the points along the wave such as points 1002. If the sampling rate is much higher than the frequency to be replicated, the signal may be replicated to any desired frequency accuracy. The polarity of the square wave at each sample instant may be stored as a binary one or zero, providing information with which to reproduce the signal for as long as desired. Unfortunately, this system is one of the least economical in the use of storage, requiring a large and costly storage capability to be functional, since there must be a number of samples per cycle of square wave in order to replicate the original signal with high accuracy. This system also requires very high sampling rates, which may be beyond the state of the art where the signal to be replicated is at a high frequency, since for example over 1000 samples per cycle of square wave is required for 0.1 percent frequency accuracy when measuring one square wave cycle.